6.5. Configuration bits
The PIC18F25K50 and PIC18F45K50 have several configuration bits in flash memory. For the P-Star, the values of those configuration bits are shown in the table below. These configuration bits cannot be changed by the bootloader or an application loaded by the bootloader; you will need to use an external programmer and erase the bootloader if you want to change any of them.
|Register name||Hex value||Binary value|
These configuration bit values can be specified using following code for the XC8 compiler:
// CONFIG1L #pragma config PLLSEL = PLL3X #pragma config CFGPLLEN = ON #pragma config CPUDIV = NOCLKDIV #pragma config LS48MHZ = SYS48X8 // CONFIG1H #pragma config FOSC = HSH #pragma config PCLKEN = OFF #pragma config FCMEN = OFF #pragma config IESO = OFF // CONFIG2L #pragma config nPWRTEN = ON #pragma config BOREN = ON #pragma config BORV = 285 #pragma config nLPBOR = ON // CONFIG2H #pragma config WDTEN = SWON #pragma config WDTPS = 256 // CONFIG3H #pragma config PBADEN = ON #pragma config SDOMX = RB3 #pragma config CCP2MX = RC1 #pragma config T3CMX = RC0 #pragma config MCLRE = ON // CONFIG4L #pragma config STVREN = ON #pragma config LVP = ON #pragma config XINST = OFF // CONFIG5L #pragma config CP0 = ON #pragma config CP1 = OFF #pragma config CP2 = OFF #pragma config CP3 = OFF // CONFIG5H #pragma config CPB = OFF #pragma config CPD = OFF // CONFIG6L #pragma config WRT0 = ON #pragma config WRT1 = OFF #pragma config WRT2 = OFF #pragma config WRT3 = OFF // CONFIG6H #pragma config WRTC = ON #pragma config WRTB = ON #pragma config WRTD = OFF // CONFIG7L #pragma config EBTR0 = ON #pragma config EBTR1 = OFF #pragma config EBTR2 = OFF #pragma config EBTR3 = OFF // CONFIG7H #pragma config EBTRB = OFF
Full documentation of these settings can be found in the PIC18F25K50/PIC18F45K50 datasheet, and some of the settings are discussed below.
The PIC18 extended instruction set is disabled, so the microcontroller uses the legacy instruction set. The legacy instruction set is the only instruction set supported by the XC8 compiler, but if you use a different compiler then you should make sure it supports the legacy instruction set and is configured to use it.
I/O pin configuration
The MCLRE bit is set to 1, so the MCLR pin is used as a reset pin and not a generic digital input.
The SDOMX bit is set to 1, so the SDO (SPI data output) pin is assigned to RB3.
The T3CMX bit is set to 1, so the T3CKI (Timer3 clock input) pin is assigned to RC0.
The CCP2MX bit is set to 1, so the CCP2 input/output pin is assigned to RC1.
The P-Star is configured to automatically use the on-board 16 MHz crystal, which is also known as the primary oscillator. The signal from the crystal goes to a PLL, which uses it to generate a 48 MHz signal for the CPU and the peripherals. The CPU takes at least 4 cycles to execute a single instruction, so it can execute up to 12 million instructions per second (12 MIPS).
The PCLKEN configuration bit is set to 0, so it is possible to shut down the primary oscillator and switch over to the internal oscillator of the PIC microcontroller. However, without changing the FOSC<3:0> configuration bits, it is not possible to clock the USB module from the internal oscillator. Also, without changing the FOSC<3:0> configuration bits, it is not possible to send the signal from the internal oscillator through the PLL, so the maximum CPU clock speed would be 16 MHz (4 million instructions per second), which is three times slower than the default.
The brown-out reset threshold on the P-Star is set to a nominal value of 2.85 V. The brown-out reset is enabled by default, but it can be disabled in software by clearing the SBOREN bit in the RCON register. The low-power brown-out reset circuit is also enabled, and will cause the microcontroller to reset at some point between 1.8 V and 2.1 V.
Clearing the SBOREN bit will reduce the power consumption of the microcontroller and will allow it to continue operating if VDD falls below 2.85 V. However, it will not be able to power up successfully from a voltage below 2.85 V, because SBOREN is set to 1 on power-up. Also, the microcontroller is not guaranteed to operate correctly below 2.7 V without switching to a slower clock source.
The watchdog timer is disabled by default, but it can be enabled by setting the SWDTEN bit in the WDTCON register. The watchdog postscaler is set to 1:256, so the watchdog timer’s period is about 1048 ms.
The region of flash memory occupied by the bootloader is write-protected to prevent accidental corruption of the bootloader. The lower 2 KB of the bootloader’s flash memory are readable and contain some useful data (as described in Section 6.1), but the rest of the bootloader is read-protected.